![]() ![]() If you happen to run something on the wrong CCD, you still run it on a fast Zen 4 core anwyay. The goal with dual CCD is to have 1 that clock very high if you run somthing that aren't cache sensitive, and one that have a lot of cache if you run something that does. Both CPU have the same instruction set and architecture and in this case is more optimisation of performance than optimisation of die size. Well, I guess they're really upset now that everyone's doing the overcomplicating.This is still way simplier than intel Big.Little solution. HisDivineOrderRemember when I read people saying how they just wanted an uncomplicated CPU that did what it did without fancy tricks? They said Alder Lake and Raptor Lake were just too complicated and using scheduler tricks was just downright uncivilized. Posted on Feb 23rd 2023, 19:19 Reply #18 Punkenjoy I don't believe for a second that AMD will solve this problem through AGESA alone, without any help from Microsoft or chipset drivers. ![]() We've seen proprietary features under the Tweaker page before (remember the dynamic OC switcher on Dark Hero that would "automatically" toggle between all-core and PBO depending on load?). ![]() The "OS agnostic" remark is pretty amusing to me - for 3 years Ryzen at every turn has been heavily dependent on complementary Windows optimizations just to work properly, and now according to random Twitter dude it's suddenly "OS agnostic"? :rolleyes:Īs for the Core Flex feature, I'm not fully convinced yet that it's an AMD-wide feature contained in AGESA. Remember the 7950X's Win 11 gaming regressions due to loads not being confined to CCD1 properly? Same deal except the stakes are even higher now. After all, how many people care about chipset driver changelogs?Probably still need some software element to make Windows scheduler function properly. ZlobbyYeah, but I expected AMD to streamline this a bit. WHQL Adds 3DV Cache Optimization 1.0.0.7 #1 VulkanBros
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